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ltc2641/ltc2642 1 26412fb typical application features applications description 16-/14-/12-bit v out dacs in 3mm 3mm dfn the ltc ? 2641/ltc2642 are families of 16-, 14- and 12-bit unbuffered voltage output dacs. these dacs operate from a single 2.7v to 5.5v supply and are guaranteed monotonic over temperature. the ltc2641a-16/ltc2642a-16 provide 16-bit performance (1lsb inl and 1lsb dnl) over temperature. unbuffered dac outputs result in low supply current of 120a and a low offset error of 1lsb. both the ltc2641 and ltc2642 feature a reference input range of 2v to v dd . v out swings from 0v to v ref . for bipolar operation, the ltc2642 includes matched scaling resistors for use with an external precision op amp (such as the lt1678), generating a v ref output swing at r fb . the ltc2641/ltc2642 use a simple spi/microwire compatible 3-wire serial interface which can be operated at clock rates up to 50mhz and can interface directly with optocouplers for applications requiring isolation. a power-on reset circuit clears the ltc2641s dac output to zero scale and the ltc2642s dac output to midscale when power is initially applied. a logic low on the clr pin asynchronously clears the dac to zero scale (ltc2641) or midscale (ltc2642). these dacs are all speci? ed over the commercial and industrial ranges. n tiny 3mm 3mm 8-pin dfn package n maximum 16-bit inl error: 1lsb over temperature n low 120a supply current n guaranteed monotonic over temperature n low 0.5nv?sec glitch impulse n 2.7v to 5.5v single supply operation n fast 1s settling time to 16 bits n unbuffered voltage output directly drives 60k loads n 50mhz spi tm /qspi tm /microwire tm compatible serial interface n power-on reset clears dac output to zero scale (ltc2641) or midscale (ltc2642) n schmitt-trigger inputs for direct optocoupler interface n asynchronous clr pin n 8-lead msop, 3mm 3mm dfn, and 8-lead so packages (ltc2641) n 10-lead msop and 3mm 3mm dfn packages (ltc2642) n high resolution offset and gain adjustment n process control and industrial automation n automatic test equipment n data aquisition systems bipolar 16-bit dac ltc2642-16 integral nonlinearity l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. C + 16-bit data latch control logic 16-bit dac 1/2 lt1678 inv r fb v dd v ref 2v to v dd bipolar v out Cv ref to v ref 0.1f 5pf ref 2.7v to 5.5v v out gnd 26412 ta01a 16-bit shift register 1f 0.1f ltc2642 power-on reset cs sclk din clr code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 26412 ta01b C0.6 0.6 0.8 0.2 49152 65535 v dd = 5v v ref = 2.5v 2.5v range inl 25c inl 90c inl C45c
ltc2641/ltc2642 2 26412fb absolute maximum ratings v dd to gnd .................................................. C0.3v to 6v cs , sclk, din, clr to gnd ........................ C0.3v to (v dd + 0.3v) or 6v ref, v out , inv to gnd ......... C0.3v to (v dd + 0.3v) or 6v r fb to inv ....................................................... C6v to 6v r fb to gnd ..................................................... C6v to 6v gnd to gnd (s8 package) ....................... C0.3v to 0.3v (note 1) ltc2641 top view 9 dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 4 3 2 1 ref cs sclk din gnd v dd v out clr t jmax = 125c (note 2), ja = 43c/w exposed pad (pin 9) is gnd, must be soldered to pcb ltc2641 1 2 3 4 ref cs sclk din 8 7 6 5 gnd v dd v out clr top view ms8 package 8-lead plastic msop t jmax = 125c (note 2), ja = 120c/w ltc2641 1 2 3 4 8 7 6 5 top view v dd gnd din sclk v out gnd ref cs s8 package 8-lead plastic so t jmax = 125c, ja = 110c/w ltc2642 top view 11 dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 gnd v dd r fb inv v out ref cs sclk din clr t jmax = 125c (note 2), ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb ltc2642 1 2 3 4 5 ref cs sclk din clr 10 9 8 7 6 gnd v dd r fb inv v out top view ms package 10-lead plastic msop t jmax = 125c (note 2), ja = 120c/w pin configuration operating temperature range ltc2641c/ltc2642c ............................... 0c to 70c ltc2641i/ltc2642i .............................. C40c to 85c maximum junction temperature (note 2)............. 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c
ltc2641/ltc2642 3 26412fb order information lead free finish tape and reel part marking* package description temperature range ltc2641acdd-16#pbf ltc2641acdd-16#trpbf lczp 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2641cdd-16#pbf ltc2641cdd-16#trpbf lczp 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2641cdd-14#pbf ltc2641cdd-14#trpbf lczn 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2641cdd-12#pbf ltc2641cdd-12#trpbf lczm 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2641aidd-16#pbf ltc2641aidd-16#trpbf lczp 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2641idd-16#pbf ltc2641idd-16#trpbf lczp 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2641idd-14#pbf ltc2641idd-14#trpbf lczn 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2641idd-12#pbf ltc2641idd-12#trpbf lczm 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2641acms8-16#pbf ltc2641acms8-16#trpbf ltczs 8-lead plastic msop 0c to 70c ltc2641cms8-16#pbf ltc2641cms8-16#trpbf ltczs 8-lead plastic msop 0c to 70c ltc2641cms8-14#pbf ltc2641cms8-14#trpbf ltczr 8-lead plastic msop 0c to 70c ltc2641cms8-12#pbf ltc2641cms8-12#trpbf ltczq 8-lead plastic msop 0c to 70c ltc2641aims8-16#pbf ltc2641aims8-16#trpbf ltczs 8-lead plastic msop ?40c to 85c ltc2641ims8-16#pbf ltc2641ims8-16#trpbf ltczs 8-lead plastic msop ?40c to 85c ltc2641ims8-14#pbf ltc2641ims8-14#trpbf ltczr 8-lead plastic msop ?40c to 85c ltc2641ims8-12#pbf ltc2641ims8-12#trpbf ltczq 8-lead plastic msop ?40c to 85c ltc2641cs8-16#pbf ltc2641cs8-16#trpbf 264116 8-lead plastic so 0c to 70c ltc2641is8-16#pbf ltc2641is8-16#trpbf 264116 8-lead plastic so ?40c to 85c ltc2642acdd-16#pbf ltc2642acdd-16#trpbf lczw 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2642cdd-16#pbf ltc2642cdd-16#trpbf lczw 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2642cdd-14#pbf ltc2642cdd-14#trpbf lczv 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2642cdd-12#pbf ltc2642cdd-12#trpbf lczt 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2642aidd-16#pbf ltc2642aidd-16#trpbf lczw 10-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2642idd-16#pbf ltc2642idd-16#trpbf lczw 10-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2642idd-14#pbf ltc2642idd-14#trpbf lczv 10-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2642idd-12#pbf ltc2642idd-12#trpbf lczt 10-lead (3mm 3mm) plastic dfn ?40c to 85c ltc2642acms-16#pbf ltc2642acms-16#trpbf ltczz 10-lead plastic msop 0c to 70c ltc2642cms-16#pbf ltc2642cms-16#trpbf ltczz 10-lead plastic msop 0c to 70c ltc2642cms-14#pbf ltc2642cms-14#trpbf ltczy 10-lead plastic msop 0c to 70c ltc2642cms-12#pbf ltc2642cms-12#trpbf ltczx 10-lead plastic msop 0c to 70c ltc2642aims-16#pbf ltc2642aims-16#trpbf ltczz 10-lead plastic msop ?40c to 85c ltc2642ims-16#pbf ltc2642ims-16#trpbf ltczz 10-lead plastic msop ?40c to 85c ltc2642ims-14#pbf ltc2642ims-14#trpbf ltczy 10-lead plastic msop ?40c to 85c ltc2642ims-12#pbf ltc2642ims-12#trpbf ltczx 10-lead plastic msop ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc2641/ltc2642 4 26412fb electrical characteristics symbol parameter conditions min typ max units reference input v ref reference input range l 2.0 v dd v r ref reference input resistance (note 5) unipolar mode (ltc2641) bipolar mode (ltc2642) l l 11 8.5 14.8 11.4 k k dynamic performancev out sr voltage output slew rate measured from 10% to 90% 15 v/s output settling time to 0.5lsb of fs 1 s dac glitch impulse major carry transition 0.5 nv?s digital feedthrough code = 0000hex; ncs = v dd ; sclk, din 0v to v dd levels 0.2 nv?s dynamic performancereference input bw reference C3db bandwidth code = ffffhex 1.3 mhz reference feedthrough code = 0000hex, v ref = 1v p-p at 100khz 1 mv p-p snr signal-to-noise ratio 92 db c in(ref) reference input capacitance code = 0000hex code = ffffhex 75 120 pf pf digital inputs v ih digital input high voltage v cc = 3.6v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v l l 0.8 0.6 v v the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v or 5v, v ref = 2.5v, c l = 10pf, gnd = 0, r l = unless otherwise specified. symbol param eter conditions ltc2641-12 ltc2642-12 ltc2641-14 ltc2642-14 ltc2641-16 ltc2642-16 ltc2641a-16 ltc2642a-16 units min typ max min typ max min typ max min typ max static peformance n resolution l 12 14 16 16 bits monotonicity l 12 14 16 16 bits dnl differential nonlinearity (note 3) l 0.5 0.5 1 0.5 1 0.5 1 lsb inl integral nonlinearity (note 3) l 0.5 0.5 1 0.5 2 0.5 1 lsb zse zero code offset error code = 0 l 1 2 2 2 lsb zs tc zero code tempco 0.05 0.05 0.05 0.05 ppm/c ge gain error l 0.5 2 1 4 2 5 2 5 lsb ge tc gain error tempco 0.1 0.1 0.1 0.1 ppm/c r out dac output resistance (note 4) 6.2 6.2 6.2 6.2 k bipolar resistor matching (ltc2642) r fb /r inv 11 1 1 ratio error (note 7) l 0.1 0.03 0.015 0.015 % bze bipolar zero offset error (ltc2642) l 0.5 2 0.5 4 2 5 2 5 lsb bzs tc bipolar zero tempco (ltc2642) 0.1 0.1 0.1 0.1 ppm/c psr power supply rejection v dd = 10% l 0.5 0.5 1 1 lsb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v or 5v, v ref = 2.5v, c l = 10pf, gnd = 0, r l = unless otherwise specified.
ltc2641/ltc2642 5 26412fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: ltc2641-16/ltc2642-16 1lsb = 0.0015% = 15.3ppm of full scale. ltc2641-14/ltc2642-14 1lsb = 0.006% = 61ppm of full scale. ltc2641-12/ltc2642-12 1lsb = 0.024% = 244ppm of full scale. electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v or 5v, v ref = 2.5v, c l = 10pf, gnd = 0, r l = unless otherwise specified. symbol parameter conditions min typ max units i in digital input current v in = gnd to v dd l 1 a c in digital input capacitance (note 6) l 310 pf v h hysteresis voltage 0.15 v power supply v dd supply voltage l 2.7 5.5 v i dd supply current, v dd digital inputs = 0v or v dd l 120 200 a p d power dissipation digital inputs = 0v or v dd , v dd = 5v digital inputs = 0v or v dd , v dd = 3v 0.60 0.36 mw mw timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v or 5v, v ref = 2.5v, c l = 10pf, gnd = 0, r l = unless otherwise specified. symbol parameter conditions min typ max units t 1 din valid to sclk setup time l 10 ns t 2 din valid to sclk hold time l 0ns t 3 sclk pulse width high l 9ns t 4 sclk pulse width low l 9ns t 5 cs pulse high width l 10 ns t 6 lsb sclk high to cs high l 8ns t 7 cs low to sclk high l 8ns t 8 cs high to sclk positive edge l 8ns t 9 clr pulse width low l 15 ns f sclk sclk frequency 50% duty cycle l 50 mhz v dd high to cs low (power-up delay) 30 s note 4: r out tolerance is typically 20%. note 5: reference input resistance is code dependent. minimum is at 871chex (34,588) in unipolar mode and at 671chex (26, 396) in bipolar mode. note 6: guaranteed by design and not production tested. note 7: guaranteed by gain error and offset error testing, not production tested.
ltc2641/ltc2642 6 26412fb typical performance characteristics integral nonlinearity (inl) integral nonlinearity (inl) vs supply (v dd ) inl vs v ref differential nonlinearity (dnl) differential nonlinearity (dnl) vs supply (v dd ) dnl vs v ref inl vs temperature dnl vs temperature bipolar zero error vs temperature code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 26412 g01 C0.6 0.6 0.8 0.2 49152 65535 ltc2642-16 v ref = 2.5v v dd = 5v v dd (v) 2 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 3 4 26412 g02 C0.6 0.6 0.8 0.2 5 6 v ref = 2.5v +inl Cinl v ref (v) 2 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 3 4 26412 g03 C0.6 0.6 0.8 0.2 5 6 v dd = 5.5v +inl Cinl code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 26412 g04 C0.6 0.6 0.8 0.2 49152 65535 ltc2642-16 v ref = 2.5v v dd = 5v v dd (v) 2 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 3 4 26412 g05 C0.6 0.6 0.8 0.2 5 6 v ref = 2.5v +dnl Cdnl v ref (v) 2 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 3 4 26412 g06 C0.6 0.6 0.8 0.2 5 6 v dd = 5.5v +dnl Cdnl temperature (c) C40 inl (lsb) 0.2 0.6 60 26412 g07 C0.2 C0.6 0 0.4 0.8 1.0 C0.4 C0.8 C1.0 C15 10 35 85 v ref = 2.5v v dd = 5v +inl Cinl temperature (c) C40 dnl (lsb) 0.2 0.6 60 26412 g08 C0.2 C0.6 0 0.4 0.8 1.0 C0.4 C0.8 C1.0 C15 10 35 85 v ref = 2.5v v dd = 5v +dnl Cdnl temperature (c) C40 bze (lsb) 1 3 60 26412 g09 C1 C3 0 2 4 5 C2 C4 C5 C15 10 35 85 v ref = 2.5v v dd = 5v
ltc2641/ltc2642 7 26412fb typical performance characteristics bipolar gain error vs temperature unbuffered zero scale error vs temperature (ltc2641-16) unbuffered full-scale error vs temperature (ltc2641-16) 14-bit integral nonlinearity (inl) (ltc2642-14) i ref vs code (unipolar ltc2641) 14-bit differential nonlinearity (dnl) (ltc2642-14) 12-bit integral nonlinearity (inl) (ltc2642-12) 12-bit differential nonlinearity (dnl) (ltc2642-12) i ref vs code (bipolar ltc2642) temperature (c) C40 bge (lsb) 1 3 60 26412 g10 C1 C3 0 2 4 5 C2 C4 C5 C15 10 35 85 v ref = 2.5v v dd = 5v temperature (c) C40 zse (lsb) 1.0 0.8 0.6 0.4 0.2 C0.2 C0.4 C0.6 C0.8 60 26412 g11 0 C1.0 C15 10 35 85 temperature (c) C40 fse (lsb) 60 26412 g12 C15 10 35 85 1.0 0.8 0.6 0.4 0.2 C0.2 0 C0.4 C0.6 C0.8 C1.0 code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 26412 g13 C0.6 0.6 0.8 0.2 12288 16383 ltc2642-14 v ref = 2.5v v dd = 5v code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 26412 g14 C0.6 0.6 0.8 0.2 12288 16383 ltc2642-14 v ref = 2.5v v dd = 5v code 0 i ref (a) 100 150 65535 26412 g15 50 0 16384 32768 49152 250 200 v ref = 2.5v code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 26412 g16 C0.6 0.6 0.8 0.2 3072 4095 ltc2642-12 v ref = 2.5v v dd = 5v code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 26412 g17 C0.6 0.6 0.8 0.2 3072 4095 ltc2642-12 v ref = 2.5v v dd = 5v code 0 i ref (a) 100 150 65535 26412 g18 50 0 16384 32768 49152 250 200 v ref = 2.5v
ltc2641/ltc2642 8 26412fb typical performance characteristics supply current (i dd ) vs temperature supply current (i dd ) vs supply voltage (v dd ) supply current (i dd ) vs v ref , v dd = 5v supply current (i dd ) vs v ref , v dd = 3v midscale glitch impulse full-scale transition full-scale settling (zoomed in) v out vs v dd = 0v to 5.5v (por function) ltc2641 supply current (i dd ) vs digital input voltage temperature (c) C40 0 i dd (a) 25 50 75 100 125 150 C15 10 35 60 26412 g19 85 v ref = 2.5v v dd = 5v v dd = 3v v dd (v) 2.5 0 i dd (a) 25 50 75 100 150 3 3.5 4 4.5 26412 g20 5 5.5 125 v ref = 2.5v digital input voltage (v) 0 0 i dd (a) 100 300 400 500 3 3.5 4 4.5 900 26412 g21 200 0.5 1 1.5 2 2.5 5 600 700 800 v dd = 5v v dd = 3v v ref (v) 1 0 i dd (a) 25 50 75 100 23 4 5 26412 g22 125 150 1.5 2.5 3.5 4.5 v dd = 5v v ref (v) 1 0 i dd (a) 25 50 75 100 1.5 2 2.5 3 26412 g23 125 150 v dd = 3v cs 5v/div v out 20mv/div code 32767 code 32768 code 32767 500ns/div 26412 g24 ltc2641-16 unbuffered c l = 10pf cs 5v/div v out 1v/div 500ns/div 26412 g25 ltc2641-16 unbuffered c l = 10pf v ref = 2.5v v dd = 5v cs 5v/div settle residue 250v/div 500ns/div ltc2641-16 v ref = 2.5v consult factory for measurement circuit 26412 g26 v out 10mv/div v dd = v ref 0v to 5.5v 2v/div 50ms/div 26412 g27 ltc2641-16 unbuffered c l = 10pf
ltc2641/ltc2642 9 26412fb pin functions ltc2641 C msop, dfn packages ref (pin 1): reference voltage input. apply an external reference at ref between 2v and v dd . cs (pin 2): serial interface chip select/load input. when cs is low, sclk is enabled for shifting in data on din. when cs is taken high, sclk is disabled, the 16-bit input word is latched and the dac is updated. sclk (pin 3): serial interface clock input. cmos and ttl compatible. din (pin 4): serial interface data input. data is applied to din for transfer to the device at the rising edge of sclk. clr (pin 5): asynchronous clear input. a logic low clears the dac to code 0. v out (pin 6): dac output voltage. the output range is 0v to v ref . v dd (pin 7): supply voltage. set between 2.7v and 5.5v. gnd (pin 8): circuit ground. exposed pad (dfn pin 9): circuit ground. must be sol- dered to pcb ground. ltc2641 C so package v out (pin 1): dac output voltage. the output range is 0v to v ref . gnd (pin 2): circuit ground. ref (pin 3): reference voltage input. apply an external reference at ref between 2v and v dd . cs (pin 4): serial interface chip select/load input. when cs is low, sclk is enabled for shifting in data on din. when cs is taken high, sclk is disabled, the 16-bit input word is latched and the dac is updated. sclk (pin 5): serial interface clock input. cmos and ttl compatible. din (pin 6): serial interface data input. data is applied to din for transfer to the device at the rising edge of sclk. gnd (pin 7): circuit ground pin. must be connected to pin 2 (gnd). v dd (pin 8): supply voltage. set between 2.7v and 5.5v. ltc2642 C msop , dfn packages ref (pin 1): reference voltage input. apply an external reference at ref between 2v and v dd . cs (pin 2): serial interface chip select/load input. when cs is low, sclk is enabled for shifting in data on din. when cs is taken high, sclk is disabled, the 16-bit input word is latched and the dac is updated. sclk (pin 3): serial interface clock input. cmos and ttl compatible. din (pin 4): serial interface data input. data is applied to din for transfer to the device at the rising edge of sclk. clr (pin 5): asynchronous clear input. a logic low clears the dac to midscale. v out (pin 6): dac output voltage. the output range is 0v to v ref . inv (pin 7): center tap of internal scaling resistors. con- nect to an external ampli? ers inverting input in bipolar mode. r fb (pin 8): feedback resistor. connect to an external ampli? ers output in bipolar mode. the bipolar output range is Cv ref to v ref . v dd (pin 9): supply voltage. set between 2.7v and 5.5v. gnd (pin 10): circuit ground. exposed pad (dfn pin 11): circuit ground. must be soldered to pcb ground.
ltc2641/ltc2642 10 26412fb block diagrams ltc2641 - msop , dfn ltc2642 16-bit data latch control logic 16-/14-/12-bit dac v dd ref v out gnd 2641 bd01a 16-bit shift register power-on reset ltc2641-16 ltc2641-14 ltc2641-12 cs sclk din clr 6 8 5 4 3 2 1 7 16-bit data latch control logic 16-/14-/12-bit dac inv r fb v dd ref v out gnd 2642 bd 16-bit shift register power-on reset ltc2642-16 ltc2642-14 ltc2642-12 cs sclk din clr 8 7 6 10 5 4 3 2 1 9 ltc2641 - so 16-bit data latch control logic 16-/14-/12-bit dac v dd ref v out gnd 2641 bd01b 16-bit shift register power-on reset ltc2641-16 cs sclk din gnd 1 2 7 6 5 4 3 8
ltc2641/ltc2642 11 26412fb operation timing diagram general description the ltc2641/ltc2642 family of 16-/14-/12-bit voltage output dacs offer full 16-bit performance with less than 1lsb integral linearity error and less than 1lsb differ- ential linearity error, guaranteeing monotonic operation. they operate from a single supply ranging from 2.7v to 5.5v, consuming 120a (typical). an external voltage reference of 2v to v dd determines the dacs full-scale output voltage. a 3-wire serial interface allows the ltc2641/ltc2642 to ? t into a small 8-/10-pin msop or dfn 3mm 3mm package. digital-to-analog architecture the dac architecture is a voltage switching mode resis- tor ladder using precision thin-? lm resistors and cmos switches. the ltc2641/ltc2642 dac resistor ladders are composed of a proprietary arrangement of matched dac sections. the four msbs are decoded to drive 15 equally weighted segments, and the remaining lower bits drive successively lower weighted sections. major carry glitch impulse is very low at 500pv?sec, c l = 10pf, ten times lower than previous dacs of this type. the digital-to-analog transfer function at the v out pin is: v out(ideal) = k 2 n v ref where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is between 2.0v and v dd (see tables 1a, 1b and 1c). the ltc2642 includes matched resistors that are tied to an external ampli? er to provide bipolar output swing (figure 2). the bipolar transfer function at the rfb pin is: v out _ bipolar(ideal) = v ref k 2 nC 1 C1 (see tables 2a, 2b and 2c). serial interface the ltc2641/ltc2642 communicates via a standard 3-wire spi/qspi/microwire compatible interface. the chip select input ( cs ) controls and frames the loading of serial data from the data input (din). following a cs t 1 sck sdi cs /ld t 5 t 7 t 2 t 6 t 8 26412 td 12 3 15 16 t 3 t 4
ltc2641/ltc2642 12 26412fb operation high-to-low transition, the data on din is loaded, msb ? r s t , in to t he shi f t r e gis ter on e ach r ising edge of t he s er ial clock input (sclk). after 16 data bits have been loaded into the serial input register, a low-to-high transition on cs transfers the data to the 16-bit dac latch, updating the dac output (see figures 1a, 1b, 1c). while cs remains high, the serial input shift register is disabled. if there are less than 16 low-to-high transitions on sclk while cs remains low, the data will be corrupted, and must be reloaded. also, if there are more than 16 low-to-high transi- tions on sclk while cs remains low, only the last 16 data bits loaded from din will be transferred to the dac latch. for the 14-bit dacs, (ltc2641-14/ltc2642-14), the msb remains in the same (left-justi? ed) position in the input 16-bit data word. therefore, two dont-care bits must be loaded after the lsb, to make up the required 16 data bits (figure 1b). similarly, for the 12-bit family members (ltc2641-12/ltc2642-12) four dont-care bits must follow the lsb (figure 1c). power-on reset the ltc2641/ltc2642 include a power-on reset circuit to ensure that the dac ouput comes up in a known state. when v dd is ? rst applied, the power-on reset circuit sets the output of the ltc2641 to zero-scale (code 0). the ltc2642 powers up to midscale (bipolar zero). de- pending on the dac number of bits, the midscale code is: 32,768 (ltc2642-16); 8,192 (ltc2642-14); or 2,048 (ltc2642-12). clearing the dac a 10ns (minimum) low pulse on the clr pin asynchro- nously clears the dac latch to code zero (ltc2641) or to midscale (ltc2642). figure 1c. 12-bit timing diagram (ltc2641-12/ltc2642-12) figure 1b. 14-bit timing diagram (ltc2641-14/ltc2642-14) figure 1a. 16-bit timing diagram (ltc2641-16/ltc2642-16) d15 msb 1 cs sclk din 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d14 d13 d12 d11 d10 d9 d8 data (16 bits) d7 d6 d5 d4 d3 d2 d1 d0 dac updated lsb 26412 f01a d13 msb 1 cs sclk din 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d12 d11 d10 d9 d8 d7 d6 data (14 bits + 2 dont-care bits) d5 d4 d3 d2 d1 d0 x x dac updated lsb 26412 f01b msb 1 cs sclk din 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d11 d10 d9 d8 d7 d6 data (12 bits + 4 dont-care bits) d5 d4 d3 d2 d1 d0 x x x x dac updated lsb 26412 f01c
ltc2641/ltc2642 13 26412fb applications information unipolar con? guration figure 2 shows a typical unipolar dac application for the ltc2641. tables 1a, 1b and 1c show the unipolar binary code tables for 16-bit, 14-bit and 12-bit operation. C + 16-bit dac 1/2 ltc6078 5v/3v 5v/3v v ref 2.5v v dd ltc2641-16 unipolar v out 0v to 2.5v 4.7f 0.1f ref 1 6 8 v out gnd 26412 f02 0.1f 0.1f 7 5 4 3 2 cs sclk din clr lt ? 1019cs8-2.5 gnd out 5v in the external ampli? er provides a unity-gain buffer. the ltc2642 can also be used in unipolar con? guration by tying r fb and inv to ref . this provides power-up and clear to midscale. table 1b. 14-bit unipolar binary code table (ltc2641-14) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 11xx v ref (16,383/16,384) 1000 0000 0000 00xx v ref (8,192/16,384) = v ref /2 0000 0000 0000 01xx v ref (1/16,384) 0000 0000 0000 00xx 0v figure 2. 16-bit unipolar output (ltc2641-16) unipolar v out = 0v to v ref table 1a. 16-bit unipolar binary code table (ltc2641-16) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 1111 v ref (65,535/65,536) 1000 0000 0000 0000 v ref (32,768/65,536) = v ref /2 0000 0000 0000 0001 v ref (1/65,536) 0000 0000 0000 0000 0v table 1c. 12-bit unipolar binary code table (ltc2641-12) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 xxxx v ref (4,095/4,096) 1000 0000 0000 xxxx v ref (2,048/4,096) = v ref /2 0000 0000 0001 xxxx v ref (1/4,096) 0000 0000 0000 xxxx 0v
ltc2641/ltc2642 14 26412fb applications information bipolar con? guration figure 3 shows a typical bipolar dac application for the ltc2642. the on-chip bipolar offset/gain resistors, r fb and r inv , are connected to an external ampli? er to produce a bipolar output swing from Cv ref to v ref at the r fb pin. the ampli? er circuit provides a gain of +2 from the v out pin, and gain of C1 from v ref . tables 2a, 2b and 2c show the bipolar offset binary code tables for 16-bit, 14-bit and 12-bit operation. C + 16-bit dac 1/2 lt1678 5v C5v 5v/3v v ref 2.5v v dd ltc2642-16 bipolar v out C2.5v to 2.5v 4.7f c1 10pf 0.1f 0.1f ref 1 6 10 v out 7 inv 8 r fb gnd 26412 f02 0.1f 0.1f 9 5 4 3 2 cs sclk din clr lt1019cs8-2.5 gnd out 5v in table 2b. 14-bit bipolar offset binary code table (ltc2642-14) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 11xx v ref (8,191/8,192) 1000 0000 0000 01xx v ref (1/8,192) 1000 0000 0000 00xx 0v 0111 1111 1111 11xx Cv ref (1/8,192) 0000 0000 0000 00xx Cv ref figure 3. 16-bit bipolar output (ltc2642-16) v out = Cv ref to v ref table 2a. 16-bit bipolar offset binary code table (ltc2642-16) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 1111 v ref (32,767/32,768) 1000 0000 0000 0001 v ref (1/32,768) 1000 0000 0000 0000 0v 0111 1111 1111 1111 Cv ref (1/32,768) 0000 0000 0000 0000 Cv ref table 2c. 12-bit bipolar offset binary code table (ltc2642-12) digital input binary number in dac latch analog output (v out ) msb lsb 1111 1111 1111 xxxx v ref (2,047/2,048) 1000 0000 0001 xxxx v ref (1/2,048) 1000 0000 0000 xxxx 0v 0111 1111 1111 xxxx Cv ref (1/2048) 0000 0000 0000 xxxx Cv ref
ltc2641/ltc2642 15 26412fb applications information unbuffered operation and v out loading the dac output is available directly at the v out pin, which swings from gnd to v ref . unbuffered operation provides the lowest possible offset, full-scale and linearity errors, the fastest settling time and minimum power consumption. however, unbuffered operation requires that appropriate loading be maintained on the v out pin. the ltc2641/ ltc2642 v out can be modeled as an ideal voltage source in series with a source resistance of r out , typically 6.2k (figure 4). the dacs linear output impedance allows it to drive medium loads (r l > 60k) without degrading inl or dnl; only the gain error is increased. the gain error (ge) caused by a load resistance, r l , (relative to full scale) is: ge = C1 1 + r out r l in 16-bit lsbs: ge = C65536 1 + r out r l
lsb r out has a low tempco (typically < 50ppm/c), and is independent of dac code. the variation of r out , part-to- part, is typically less than 20%. note on lsb units: for the following error descriptions, lsb means 16-bit lsb and 65,536 is rounded to 66k. to convert to 14-bit lsbs (ltc2641-14/ltc2642-14) divide by 4. to convert to 12-bit lsbs (ltc2641-12/ltc2642-12) divide by 16. a constant current, i l , loading v out will produce an offset of: v offset = Ci l ? r out for v ref = 2.5v, a 16-bit lsb equals 2.5v/65,536, or 38v. since r out is 6.2k, an i l of 6na produces an offset of 1lsb. therefore, to avoid degrading dac performance, it is critical to protect the v out pin from any sources of leakage current. unbuffered v out settling time the settling time at the v out pin can be closely approxi- mated by a single-pole response where: = r out ? (c out + c l ) (figure 4). settling to 1/2lsb at 16-bits requires about 12 time constants (ln(2 ? 65,536)). the typical settling time of 1s corresponds to a time constant of 83ns, and a total (c out + c l ) of about 83ns/6.2k = 13pf . the internal capacitance, c out is typically 10pf, so an external c l of 3pf corresponds to 1s settling to 1/2lsb. i l v out 0v to v ref r out v out c out ltc2641 ltc2642 v ref ref gnd code 2 n v ref () c l 26412 f04 r l + C figure 4. v out pin equivalent circuit op amp selection the optimal choice for an external buffer op amp depends on whether the dac is used in the unipolar or bipolar mode of operation, and also depends on the accuracy, speed, power dissipation and board area requirements of the application. the ltc2641/ltc2642s combination of tiny package size, rail-to-rail single supply operation, low power dissipation, fast settling and nearly ideal accuracy speci? cations makes it impractical for one op amp type to ? t every application. in bipolar mode (ltc2642 only), the ampli? er operates with the internal resistors to provide bipolar offset and scaling. in this case, a precision ampli? er operating from dual power supplies, such as the the lt1678 provides the v ref output range (figure 3). in unipolar mode, the output ampli? er operates as a unity gain voltage follower. for unipolar, single supply applica- tions a precision, rail-to-rail input, single supply op amp
ltc2641/ltc2642 16 26412fb applications information such as the ltc6078 is suitable, if the application does n o t r e q u i r e l i n e a r o p e r a t i o n v e r y n e a r t o g n d, o r z e r o s c a l e (figure 2). the ltc6078 typically swings to within 1mv of gnd if it is not required to sink any load current. for an lsb size of 38v, 1mv represents 26 missing codes near zero scale. linearity will be degraded over a somewhat larger range of codes above gnd. it is also unavoidable that settling time and transient performance will degrade whenever a single supply ampli? er is operated very close to gnd, or to the positive supply rail. the small lsb size of a 16-bit dac, coupled with the tight accuracy speci? cations on the ltc2641/ltc2642, means that the accuracy and input speci? cations for the external op amp are critical for overall dac performance. op amp speci? cations and unipolar dac accuracy most op amp accuracy speci? cations convert easily to dac accuracy. op amp input bias current on the noninverting (+) input is equivalent to an i l loading the dac v out pin and therefore produces a dac zero-scale error (zse) (see unbuffered operation): zse = Ci b (in+) ? r out [volts] in 16-bit lsbs: zse = Ci b in + () ? 6.2k ? 66k v re f
lsb op amp input impedance, r in , is equivalent to an r l loading the ltc2641/ltc2642 v out pin, and produces a gain error of: ge = C66k 1 + 6.2k r i n
lsb op amp offset voltage, v os , corresponds directly to dac zero code offset error, zse: zse v k v lsb os ref = [] ? 66 temperature effects also must be considered. over the C40c to 85c industrial temperature range, an offset voltage temperature coef? cient (referenced to 25c) of 0.6v/c will add 1lsb of zero-scale error. also, i bias and the v offset error it causes, will typically show signi? cant relative variation over temperature. op amp open-loop gain, a vol , contributes to dac gain error (ge): ge k a lsb vol = [] 66 op amp input common mode rejection ratio (cmrr) is an input-referred error that corresponds to a combina- tion of gain error (ge) and inl, depending on the op amp architecture and operating conditions. a conservative estimate of total cmrr error is: error = 10 cmrr 2 0

? v cmrr _range v re f
? 66k lsb where v cmrr_range is the voltage range that cmrr (in db) is speci? ed over. op amp typical performance charac- teristics graphs are useful to predict the impact of cmrr errors on dac performance. typically, a precision op amp will exhibit a fairly linear cmrr behavior (corresponding to dac gain error only) over most of the common mode input range (cmr), and become nonlinear and produce signi? cant errors near the edge of the cmr. rail-to-rail input op amps are a special case, because they have 2 distinct input stages, one with cmr to gnd and the other with cmr to v + . this results in a crossover cm input region where operation switches between the two input stages. the ltc6078 rail-to-rail input op amp typically exhibits remarkably low crossover linearity error, as shown in the v os vs v cm typical performance characteristics graphs (see the ltc6078 data sheet). crossover occurs at cm inputs about 1v below v + , and an ltc6078 operating as a unipolar dac buffer with v ref = 2.5v and v + = 5v will typically add only about 1lsb of ge and almost no inl error due to cmrr. even in a full rail-to-rail application, with v ref = v + = 5v, a typical ltc6078 will add only about 1lsb of inl at 16-bits.
ltc2641/ltc2642 17 26412fb op amp speci? cations and bipolar dac accuracy the op amp contributions to unipolar dac error discussed above apply equally to bipolar operation. the bipolar ap- plication circuit gains up the dac span, and all errors, by a factor of 2. since the lsb size also doubles, the errors in lsbs are identical in unipolar and bipolar modes. one added error in bipolar mode comes from i b (in C ), which ? ows through r fb to generate an offset. the full bias current offset error becomes: v offset = (i b (in C ) ? r fb C i b (in + ) ? r out ? 2) [volts] so: v i in k i in k k v offset b b ref = () + ()? C()?.? C 28 12 4 33 [] lsb settling time with op amp buffer when using an external op amp, the output settling time will still include the single pole settling on the ltc2641/ ltc2642 v out node, with time constant r out ? (c out + c l ) (see unbuffered v out settling time). c l will include the buffer input capacitance and pc board interconnect capacitance. the external buffer ampli? e r a d d s a n o t h e r p o l e t o t h e o u t p u t response, with a time constant equal to (fbandwidth/2 ). for example, assume that c l is maintained at the same value as above, so that the v out node time constant is 83ns = 1s/12. the output ampli? er pole will also have a time constant of 83ns if the closed-loop bandwidth equals (1/2 ? 83ns) = 1.9mhz. the effective time constant of two cascaded single-pole sections is approximately the root square sum of the individual time constants, or 2 ? 83ns = 117ns, and 1/2 lsb settling time will be ~12 ? 117ns = 1.4s. this represents an ideal case, with no slew limiting and ideal op amp phase margin. in practice, it will take a considerably faster ampli? er, as well as careful attention to maintaining good phase margin, to approach the unbuffered settling time of 1s. the output settling time for bipolar applications (figure 3) will be somewhat increased due to the feedback resistor network r fb and r inv (each 28k nominal). the parasitic capacitance, c p , on the op amp (C) input node will introduce a feedback loop pole with a time constant of (c p ? 28k/2). a small feedback capacitor, c1, should be included, to introduce a zero that will partially cancel this pole. c1 should nominally be ltc2641/ltc2642 18 26412fb as the external reference remains stable with the added capacative loading. digital inputs and interface logic all of the digital inputs include schmitt-trigger buffers to accept slow transition interfaces. this means that op- tocuplers can interface directly to the ltc2641/ltc2642 without additional external logic. digital input hysteresis is typically 150mv. the digital inputs are compatible with ttl/cmos-logic levels. however, rail-to-rail (cmos) logic swings are preferred, because operating the logic inputs away from the supply rails generates additional i dd and gnd current, (see typical performance characteristic graph supply current vs logic input voltage). digital feedthrough is only 0.2nv?s typical, but it is always preferred to keep all logic inputs static except when loading a new code into the dac. board layout for precision even a small amount of board leakage can degrade ac- curacy. the 6na leakage current into v out needed to generate 1lsb offset error corresponds to 833m leakage resistance from a 5v supply. the v out node is relatively sensitive to capacitive noise coupling, so minimum trace length, appropriate shielding and clean board layout are imperative here. temperature differences at the dac, op amp or reference pins can easily generate tens of microvolts of thermo- couple voltages. analog signal traces should be short, close together and away from heat dissipating compo- nents. air currents across the board can also generate thermocouples. the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. a star ground area should be established by attaching the ltc2641/ltc2642 gnd pin, v ref gnd and the dac v out gnd reference terminal to the same area on the gnd plane. care should be taken to ensure that no large gnd return current paths ? ow through the star gnd area. in particular, the resistance from the ltc2641 gnd pin to the point where the v ref input source connects to the ground plane should be as low as possible. excessive resistance here will be multiplied by the code dependent i ref current to produce an inl error similar to the error produced by v ref source resistance. for the ltc2641 in the s8 package both gnd pins, pin 2 and pin 7 should be tied to the same gnd plane. sources of ground return current in the analog area include op amp power supply bypass capacitors and the gnd connection for single supply amps. a useful technique for minimizing errors is to use a separate board layer for power ground return connections, and reserve one ground plane layer for low current signal gnd connec- tions. the signal, or star gnd plane must connected to the power gnd plane at a single point, which should be located near the ltc2641/ltc2642 gnd pin. if separate analog and digital ground areas exist it is neces- sary to connect them at a single location, which should be fairly close to the dac for digital signal integrity. in some systems, large gnd return currents can ? ow between the digital and analog gnds, especially if different pc boards are involved. in such cases the digital and analog ground connection point should not be made right at the star gnd area, so the highly sensitive analog signals are not corrupted. if forced to choose, always place analog ground quality ahead of digital signal ground. (a few mv of noise applications information
ltc2641/ltc2642 19 26412fb package description 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) applications information on the digital inputs is imperceptible, thanks to the digital input hysteresis) just by maintaining separate areas on the gnd plane where analog and digital return currents naturally ? ow, good results are generally achieved. only after this has been done, it is sometimes useful to interrupt the ground plane with strategically placed slots, to prevent the digital ground currents from fringing into the analog portion of the plane. when doing this, the gap in the plane should be only as long as it needs to be to serve its purpose. caution: if a gnd plane gap is improperly placed, so that it interrupts a signi? cant gnd return path, or if a signal traces crosses over the gap, then adding the gap may greatly degrade performance! in this case, the gnd and signal return currents are forced to ? ow the long way around the gap, and then are typically channeled directly into the most sensitive area of the analog gnd plane.
ltc2641/ltc2642 20 26412fb 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) package description
ltc2641/ltc2642 21 26412fb s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) package description .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc2641/ltc2642 22 26412fb package description msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 C 6 typ detail a detail a gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
ltc2641/ltc2642 23 26412fb information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e) package description
ltc2641/ltc2642 24 26412fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 1008 rev b ? printed in usa related parts typical application part number description comments dacs ltc1588/ltc1589 ltc1592 12-/14-/16-bit softspan tm current output dacs software programmable output ranges up to 10v ltc1595/ltc1596 serial 16-bit current output dacs low glitch, 1lsb maximum inl, dnl ltc1591/ltc1597 parallel 14-/16-bit current output dacs 1lsb max inl, dnl, 10v output ltc1599 16-bit current output dac 1lsb max inl, dnl, 10v output ltc1650 16-bit voltage output dac 2nv?s glitch impulse, 30nv/hz noise ltc2621/ltc2611 ltc2601 12-/14-/16-bit serial voltage output dacs single dacs, single supply, 0v to 5v outputs in dfn10 ltc2704-12 ltc2704-14 ltc2704-16 12-/14-/16-bit quad voltage output dacs software programmable output ranges up to 10v, serial i/o op amps lt ? 1678 dual low noise rail-to-rail precision op amp 3.9nv/hz at 1mhz ltc2054 micropower zero drift op amp 3v maximum offset lt6010 150a 8nv/hz rail-to-rail output precision op amp micropower ltc6078 dual cmos rail-to-rail input/output ampli? er 54a per amp, 16nv/hz input noise voltage references lt1019 precision bandgap reference 0.005% max, 5ppm/c max softspan is a trademark of linear technology corporation. wide range current load sinks 0a to 2.5a C + 16-bit dac ltc2054hv 10v v ref 2.5v 1k i sink 0a to 2.5a 5v v dd ltc2641-16 4.7f 0.1f 0.033f 1 10w irlz44 ref 1 6 8 v out gnd 26412 ta02 0.1f 0.1f 7 5 4 3 2 cs sclk din clr lt1019cs8-2.5 gnd out 5v in 10k

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